The present invention relates to a microprocessor system and, more particularly, to a microprocessor system for performing data transfer with another system through a multi-system bus.
A multi-system bus system is employed to arrange a system for causing a plurality of microprocessor systems to perform data transfer or a system including a slave system for passively performing data transfer under the control of another system. Known conventional multi-system buses are a 16-bit IEEE 796 bus and a 32-bit VME (Versa Module European) bus. If a system arranged by utilizing such a multi-system bus it is called a multi-system, and the multi-system has an arrangement, as shown in FIG. 2.
The multi-system shown in FIG. 2 includes three microprocessor systems 310, 320, and 330 and one slave system 340 connected to the microprocessor systems 310, 320, and 330 through a multi-system bus 300. The slave system 340 comprises a memory circuit 341 and a buffer circuit 342 and can be simultaneously accessed by the three microprocessor systems 310, 320, and 330. Each of the three microprocessor systems 310, 320, and 330 has master and slave modes. A priority is assigned to a microprocessor system set in the master mode to use or occupy the multi-system bus. A microprocessor system set in the slave mode performs a subordinate operation. More specifically, a microprocessor system set in the master mode exchanges data with a microprocessor system set in the slave mode or the slave system 340.
The three microprocessor systems 310, 320, and 330 basically comprise central processing units (CPUs) 311, 321, and 331, buffer circuits 312, 322, and 332, local 10 systems 313, 323, and 333, buffer circuits 314, 324, and 334, and bus access control circuits 315, 325, and 335, respectively. The local systems 313, 323, and 333 include CPUs, memory circuits, and I/0 devices, and perform predetermined operations under the direct control of the CPUs 311, 321, and 331, respectively. The local systems 313, 323, and 333 output bus access request signals to the bus access control circuits 315, 325, and 335 upon reception of commands from the CPUs 311, 321, and 331 when the CPUs 311, 321, and 331 access the multi-system bus 300. A bus access control signal 301 on the multi-system bus 300 is supplied to the bus access control circuits 315, 325, and 335 to determine a master-slave relationship among the three microprocessor systems. An address signal, a data signal, and a control signal are output onto the multi-system bus 300. A timing chart of this multi-system is shown in FIG. 3.
Of the three microprocessor systems, the microprocessor system 310 has a basic arrangement. The microprocessor system 320 additionally includes a slave system comprising an I/0 device 326 and a slave buffer circuit 327. This slave system is controlled through the multi-system bus 300 in the same manner as the slave system 340 and cannot be directly controlled by the CPU 321. The microprocessor system 330 additionally includes a bidirectional control circuit 336, a memory circuit 337, a decoder 338, and a slave buffer circuit 339. The memory circuit 337 is directly controlled by the CPU 331 and can be accessed by CPUs of other systems through the multi-system bus 300. The additional components of the system 330 similarly constitute a slave system.
Microprocessor systems as an object of the present invention are those having slave systems, e.g., the microprocessor systems 320 and 330. However, a conventional microprocessor system having a slave system is arranged, as shown in FIG. 4.
Referring to FIG. 4, output and input/output buses of a CPU 20 are connected to a control signal buffer circuit 21, an address signal buffer circuit 22, and a data signal buffer circuit 23. Of multi-system buses 34, a bus access control signal bus is connected to a bus access control circuit 27; a control signal bus is connected to a control signal buffer circuit 28 and a slave control signal buffer circuit 32; an address bus is connected to an address signal buffer circuit 29 and a slave address signal buffer circuit 35; and a data bus is connected to data signal buffer circuits 30a and 30b, a swap buffer circuit 31, and a slave data signal buffer circuit 33. The control signal buffer circuits 21 and 28 are connected to each other through the control signal bus. The address signal buffer circuits 22 and 29 are connected to each other through the address bus. The data signal buffer circuits 23 and 30a are connected through the data bus as are the data signal buffer circuit 30b and the swap buffer circuit 31. These buses as local system buses 24 are connected to a local system 43. The slave control signal buffer circuit 32, the slave address signal buffer circuit 35, and the slave data signal buffer circuit 33 are connected to a slave system 44 through slave system buses 26.
The local system 43 decodes a control signal sent through the control signal bus and generates a multi-system bus access request signal 40. The multi-system bus access request signal 40 is supplied to the bus access control circuit 27 and the buffer control circuit 25. The bus access control circuit 27 determines whether the multi-system buses 34 are accessed in the master or slave mode. The bus access control circuit 27 generates a multi-system bus access enable signal 41 on the basis of the determination result. The signal 41 is supplied to the buffer control circuit 25. The buffer control circuit 25 performs input/output control of the control signal buffer circuit 28, the address signal buffer circuit 29, the data signal buffer circuits 30a and 30b, and the swap buffer circuit 31 in accordance with the content of the input multi-system bus access enable signal 41, thereby achieving data transfer through the multi-system buses 34.
Even if the multi-system bus 34 is a 16-bit IEEE796 bus, the number of bits processed by the CPU of each microprocessor system is not 16 in all systems, but is normally an arbitrary number such as eight in some systems. The microprocessor system of this type includes the swap buffer circuit 31 for performing conversion between a bit width processed by the CPU of the system and a transfer bit width of the multi-system bus 34. In this case, the swap buffer circuit 31 is directly connected to the multi-system bus 34, as shown in FIG. 4.
As is apparent from the conventional microprocessor system, as shown in FIG. 4, since the buffer circuit (multi-system bus buffer circuit) for interfacing the microprocessor system with the multi-system bus is connected in parallel with the buffer circuit (slave buffer circuit) for interfacing the slave system with the multi-system bus, the following problems occur.
The data signal buffer circuits 30a and 30b, the swap buffer circuit 31, and the slave data signal buffer circuit 33 are connected in parallel with the data bus of the multi-system buses. Since a plurality of microprocessor systems and the like are connected to the multi-system buses, an n x m (where n is the number of microprocessor systems, and m is the number of parallel-connected buffer circuits) load acts on the multi-system buffer circuit of the microprocessor system operated in the master mode. This overload causes degradation of waveform and limitations of a DC fan-out count, thereby complicating system design.
The multi-system buffer circuit and the slave buffer circuit are mounted on a single printed circuit board and are connected through wiring patterns. In this case, the number of circuits is large, the pattern lengths are undesirably increased, and pattern designing becomes cumbersome.
Since the wiring pattern length is increased, noise generated from the interior of the microprocessor system is induced on the pattern and appears on the multi-system bus, thus degrading the overall operation of the system. The microprocessor system tends to be adversely affected by noise appearing on the multi-system bus.